SSS3403 p-channel enhancement mode mosfet product summary v ds (v ) i d (a ) -30v -3.4 a r ds(on) (m ? ) max 45 @v gs = -10v 80 @v gs = -4.5 v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice . south sea semiconductor , january 2008 (rev 2.2) 1 absolute maximum ra tings (t a = 25 c unless otherwise noted) therma l characteristics parameter symbol limi t unit o drain-source v oltage gate-source v oltage drain current-continuous @ t j = 25 c -pulse d drain-source diode forward current maximum power dissipatio n operating junction and storage t emperature range thermal resistance, junction-to-ambient o a a a b v ds v gs i d i dm i s p d t j , t st g r ja -3 0 v v a a a c/ w w c o o 20 - + -3.4 -1 2 -1.2 5 1.25 -55 to 150 100 so t- 23 d g s d g s fea tures super high density cell design for low r ds(on) . rugged and reliable. so t- 23 package. pb free.
SSS3403 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.2) 2 electrical characteristics (t a = 25 c unless otherwise noted) o unit symbol paramete r condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv ds s i ds s i gs s v gs(th) r ds(on) v gs =0v , i d =-250 a v ds =-24v , v gs =0v v gs = 20v , v ds =0v v ds =v gs i d =-250 a v gs =-10v , i d =-3a v gs =-4.5v , i d =-2a m v v a na -3 0 1 100 45 8 0 -1.2 on-state drain current forward tr ansconductanc e tu rn-on delay t im e rise t im e tu rn-of f delay t im e fall ti me i d(on) g fs t d(on) t r t d(off) t f v ds =-5v , v gs =-10v v ds =-5v , i d =-3a v dd =-10 v, v gs =-4.5v , r l =10 5 7 13. 5 53 37. 5 7. 5 ns p f s a input capacitanc e output capacitanc e reverse t ransfer capacitanc e c is s c os s c rs s v ds =-15v v gs =0v f=1.0mhz 812 210 153 to tal gate charge q g 7. 5 i d =-1a, r ge n =6 , nc -1.9 v -1.2 -0.7 5 2. 2 2. 5 v gs =0v , i d =-1.25a i d =-3a, v gs =-4.5v v sd q gs q gd diode forward vo ltage gate-source charge gate-drain charge v ds =-10 v, notes a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2%. c. guaranteed by design, not subject to production testing. - - - 38 70 -3
SSS3403 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.2) 3 -v ds , drain-to-source vo ltage (v ) i - d ) a ( t n e r r u c n i a r d , figure 1. output characteristics 0 0.5 1 1.5 2 2.5 3 20 16 12 8 4 0 -v gs = 2v -v gs , gate-to-source vo ltage (v ) i - d u c n i a r d , ) a ( t n e r r figure 2. t hansfer characteristics 0 0.5 1 1.5 2 2.5 3 25 20 15 10 5 0 - 5 5 c o 25 c o tj = 125 c o r , ) n o ( s d e c n a t s i s e r - n o ( d e z i l a m r o n ) -55 -25 0 25 50 75 100 125 2. 2 1. 8 1. 4 1.0 0.6 0.2 0 figure 4. on-resistance v ariation with t emperature v gs = -4.5 v t j , junction t empertature ( c ) o v gs = -2.3 a -v ds , drain-to-source vo ltage (v ) ) f p ( e c n a t i c a p a c , c figure 3. capacitance 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 1250 0 1000 750 500 250 d e z i l a m r o n , h t v e g a t l o v d l o h s e r h t e c r u o s - e t a g tj , junction te mperature ( c) figure 5. gate threshold va riatio n with t emperature o -50 -25 0 25 50 75 100 125 v ds = v gs i d = -250 a 1. 3 1. 2 1. 1 1. 0 0. 9 0. 8 0. 7 0 v b s s d d e z i l a m r o n , g a t l o v n w o d k a e r b e c r u o s - n i a r d e figure 6. breakdown v oltage v ariation with t emperature tj , junction t emperature ( c ) o -50 -25 0 25 50 75 100 125 1.10 1.07 1.04 1.0 0 0.9 7 0.9 4 0.91 i d = -250 a -v gs = 3v -v gs = 4v -v gs = 10, 9, 8, 7, 6, 5 v
SSS3403 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.2) 4 -i ds , drain-source current (a ) g , s f ) s ( e c n a t c u d n o c s n a r t 0 5 10 15 20 2 5 figure 7. t ransconductance va riation with drain current v ds = -5 v i - s ) a ( t n e r r u c n i a r d - e c r u o s , 20. 0 -v sd , body diode forward vo ltage (v ) figure 8. body diode forward vo ltage v ariation with source current 0.0 0.4 0.8 1.2 1.6 2.0 v - s g ) v ( e g a t l o v e c r u o s o t e t a g , figure 9. gate charge qg , t otal gate charge (nc) 0 2 4 6 8 10 12 14 16 10 8 6 4 2 0 v ds = -10v i d = -3 a i d ) a ( t n e r r u c n i a r d , 0.01 -v sd , drain-to-source vo ltage (v ) figure 10. maximum safe operating a rea 0.1 1 10 30 5 0 5 0 1 0 1 0.1 v gs = -10v single puls e t a = 25 c o r d s ( o n ) l i m i t 12 1 0 8 6 4 2 0 10. 0 t j = 25 c o 1.0 1 0 0 m s 1 0 m s 1s d c
SSS3403 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 2.2) 5 figure 1 1. switching t est circuit v gs r ge n v ou t v dd v in d r l g s figure 12. switching w aveforms inver ted pulse width t r t d(on) v ou t v in t on t of f t d(of f) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized t hermal t ransient impedance curve t1 t2 p dm 1. r ja(t) = r(t)* r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0. 1 10 r e v i t c e f f e d e z i l a m r o n , ) t ( e c n a d e p m i l a m r e h t t n e i s n a r t duty cycle = 0. 5 square w ave pulse duration (sec) 10 10 2 10 3 0. 2 0. 1 0.0. 5 0.02 0.01 single puls e
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